Resume 2

Objective

Analog /Mixed-Signal Design Engineer position emphasizing design and development for deep sub-micron analog circuits, PLLs, VCOs, and mixed signal circuits.

Working as a Design engineer in the PLL Design Group, with responsibilities in PLL design, Supervision of Layout, Silicon Debug & Characterization of PLL.

• Designed a PLL for DSP Processor

  Designed a PLL for DSP processor, in 0.18um technology, working at 1.8V .The VCO output frequency range was from 300Mhz to 400MHz. The input frequency range was from 11.289MHz - 27MHz. The PLL used a current starved ring oscillator. My major responsibilities were the design and simulations of the individual PLL blocks using H-spice, closed loop simulations using AMS Antrim Mixed Simulator , stability analysis using a macro-model of PLL, and post layout simulations with extracted parasitics using Arcadia.

• Designed and Debugged a PLL for 192KHz Digital Audio Interface Receiver

  Designed PLL for Audio Applications in 0.35um technology, working at 3.0V . The VCO output frequency range was from 8Mhz to 50MHz. The input frequency range was from 8KHz - 192KHz. The PLL used a relaxation type Oscillator, PFD, charge-pump, band-gap current source, and bias current generator.

  Also designed a frequency detector for the same chip, which detects whether the input sample rate frequency is greater or lower than 96KHz. - My major responsibilities for this PLL were block level simulations using H-spice, closed loop simulations using AMS Antrim Mixed Simulator , stability analysis using macro-model of PLL, and post layout simulations. Debugged the PLL using an AP BOX, network analyzer, and Time Interval Analyzer TIA , Micro-probe station, Therostream.

• Chip-Level Simulation

  Made set-up for chip level simulation using AMS Antrim Mixed Signal Simulator . Successfully simulated Audio Receiver Chip , which includes PLL, digital logic, pads. - Major challenges were to interface between digital logic and analog blocks.

• Characterized and Debugged a PLL for 96KHz Digital Audio Interface Receiver

  Characterized the performance of a PLL over temperature and voltage. RMS Cycle-Cycle Jitter, VCO gain, Time Deviation were the major things to observe.

• Designed a PLL for Cell-Phone Applications

  Designed and characterized a PLL in silicon for a cellular phone chip in 0.13u working at 220Mhz. Designed of current reference, current-controlled oscillator, DAC and PFD. The purpose of current reference block was to provide a reference current to DAC and VCO.

• The 5 bit DAC was to generate an output current corresponding to the setting of the input bits, which in turn controlled the frequency of the VCO. Variations on the output current of current reference block due to power supply, temperature and process were very small. DAC is voltage to current converter and the output current has binary weight according to input bit. All the blocks were simulated in both SSIM and BSIM models. To know the dynamic behavior of PLL digital and analog blocks are simulated in mixed signal environment Verimix . My responsibility was to setup for interface between digital and analog blocks. Digital simulations were performed using Verilog-XL and the analog simulations were done in SPICE.

• Custom Layout & Integration of Analog blocks

  Experience in full custom layout of a current reference, DAC, and VCO for a PLL in 0.18u. Experience in floor planning and integration of analog blocks. Also checked out GDSII for TESTCHIP for process qualification. This included all analog blocks with other structures like op-amps and voltage references. Also was responsible for post layout simulations using STAR-RC for parasitic extraction.

• Topology selection for analog circuit design and design of various Op-amps Proposed and implemented a methodology for analog design automation. Circuits used to verify the proposed methodology were CMOS OTA , folded cascode OTA, and Miller compensated OTA. Depending upon knowledge base and Specifications given by the user. The tool gives first hand sized-schematic diagram from the given user specifications. The source code was written in C.

Indian Institute of Technology IIT , Kanpur, India
Masters Kanpur, UP, India
Electrical Engineering Microelectronics and VLSI Design

Regional Engineering College REC
June 1998 Bechlors Hamirpur, Himachal, India
Electronics & Communication Engineering

• SPICE.
• PowerMill Synopsis circuit simulator .
• AMS Antrim mixed signal Simulator .
• MATLAB.
• Virtuoso Cadence Layout & Schematic Editor .
• Verimix Cadence Mixed Signal Simulator .
• Avanti Hercules & Mentor Caliber DRC & LVS .
• StarRC Post Layout
• Arcadia Synopsis parasitic extraction .
• Languages - Verilog.