Resume 10

Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth.

• H/W Description Languages: VHDL, Verilog.
• Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance.
• Synthesis: Exemplar logic (Leonardo Spectrum).
• Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms).
• Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.
• Languages: C, C++, perl, Unix Internals like Shell and Awk.
• Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98.
• Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF
• Others: PCI.
• Revision Control: CVS.

As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.

Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage.

• Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy.
• Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments.
• Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality.
• Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c .
• Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment.
• Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block.
• Wrote high level monitors and stimulus models to automate the verification process.
• Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform.
• Wrote Scripts for HEP (Hardware Emulation Platform) regression suites.
• Participated in estimating verification development schedules and ensured on time delivery.

As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the digital portion of the chip for television.

• Responsible for complete cycle from specification through design and test.
• Designed the digital circuit using VHDL.
• Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.
• Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA.
• Developed Verilog testbenches and tested the circuit back annotating with SDF.
• Checked the timing of the design generating test vectors for testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL.
• I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface.
• Designed a I2C bus slave interface controller using Visual HDL.
• Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.
• Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and tested the read channel chip.
• Worked on three different versions of the read channel.
• Designed the FPGA using Visual HDL generating the RTL for the design.
• Tested the design writing VHDL test benches for the proper operation
• Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.
• Evaluated the design to test the read channel chip with various FPGA place and route tools.
• Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.
• Designed an IEEE standard TAP controller.
• Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL.
• Simulated it using Modelsim. Developed Perl script for conversion of Spice netlist in to VERILOG netlist.
• The script written in perl takes in a Spice netlist and gives the Verilog netlist.
• Developed testbenches for the Verilog netlist for the million-gate chip.
• Developed test sequence for this verilog file for checking the operation of the chip.

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000.
GPA: 3.727/4.0.

Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming.

• Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects
• Design of a Linear Interpolation Filter using Verilog and full custom IC layout.
• Design of a Simple Educational Processor using VHDL.
• Designed and simulated a sigmadelta modulator for an EEG IC.

Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998.
GPA: 80.5%