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Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol.

• Hardware Description Languages: Verilog, VHDL
• High Level Verification Language: Synopsis VERA
• CVE: Mentor Graphics Co-Verification Environment
• Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell
• Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C
• OS: Sun Solaris, Unix, Windows 95/NT

Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . These modes are the local bus types. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed.

Environment: Verilog, Sun Solaris

Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors.

Environment: Verilog, CVE, Assembly, Sun Solaris 2.x

The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules.

The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs.

Environment: Verilog, VERA, VCS, Sun Solaris 2.x

Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC. Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes.

Environment: Verilog, Assembly, VCS, Unix

Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs.

Environment: Verilog, Verilog -XL, Sun Solaris 2.x

Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC. Synthesized the HDLC.

Environment: Verilog, Verilog-XL, Sun Solaris 2.x

Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation.

Environment: VHDL, Quick HDL, Unix

This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made.

Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix

Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard.

Environment: Assembly, Unix