Resume 13

To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place & route, FPGA and CHIP layout.

• VLSI Logic design - Complete design flow from RTL to layout.
• Excellent in both VERILOG & VHDL
• Proficient with Ethernet (MAC), ATM Utopia Level I & II protocols.
• Complete understanding in architectures of PCI & OHCI.
• Proficient with USB.
• Knowledge in Unix, Perl and 'C'.
• Knowledge in VERILOG PLI CONCEPTS.
• Good experience in Digital synthesis and Place & Route.
• Configuring CPLD with bit blaster using MAX+plus II.
• Expertise in Altera /APEX FPGA.
• Experience in Assembly Language.
• Analyzed circuits using SPICE.

• Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL & Verilog), Leapfrog Simulation for VHDL & Accolade Peak VHDL tools.
• Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity.
• P & R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics.
• Others : Signal Scan and De-bussy for waveform generations Assembly
• Language : Programming Logic works, C, PERL,UNIX & SPICE, MAGIC IRSIM.
• 'C' Compiler : Green Hills Software

Company I : Analog Systems, CA.
Duration : Jan '00 - Till Date
Designation : Member Of Technical Staff

Company II : Trenton Chip Devices, Inc., CA
Duration : May '99 - Dec '99
Designation : VLSI Design Engineer

Company III : Trenton Chip Devices, India
Duration : May '97 - Apr '99
Designation : VLSI Design Engineer

Profile I :

Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution
Duration : August 2000 - Till Date.

The Si was taped out on Oct '2001. The Total No. of gates is 1.2 Millions. It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small & Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP & VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system.

It is having 3 processors namely Control Processor Engine, Wan Processor Engine & Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, & SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI & USB. It has on chip SDRAM controller & flash controller 200KB of on-chip memory for voice and data processing.

• Developed & Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams.
• Created Testbenchs for the blocks like UART, SPI & DMA.
• Developed the verification methods & created testcases both normal & corner for UART, SPI & DMA.
• Did the RTL & netlist simulation for UART, SPI, DMA.
• Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL & netlist level simulations.
• Did the random testing for the above blocks at the system levels and also for the other blocks.

Tools Used :

Project : UMAC Design
Duration : Feb' 00 - July '00.

Designed, developed & verified the UMAC in VERILOG. This s going to be used and cable modem chip. The design was target for APEX FPGA from altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.

The PHY interface can get the data from simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module.

The design operates in 3 different frequencies. The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz.

Verilog XL from Cadence 2.37 & Signal Scan/De-bussy for waveforms. Max-Plus II for P & R. Synthesis by Syniplify from synplicity.

Project : SPI Design
Duration : Jan '00.

Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA.

Tools Used :

Profile II :

Project : Transceiver Subsystem
Duration : Nov'99 - Dec '99

Designed & Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the code in Verilog.

Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics

Project : Internet Data Storage
Duration : Aug'99 - Oct'99

To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated.

The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Developed & Designed the logic in verilog which is specific to Disk Module and it provides the following functions:

• Raid Parity generation
• Raid Parity verification
• Raid Parity reconstruction
• Interface to the Main Memory DMA

Compiled and simulated in MTI Verilog simulator (Model Tech).

Project : OC3_FPGA
Duration : May'99 - July'99

The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported.

• Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target.
• Module ware Utopia Master and Slave.
• Interface Data Path Between Tetra and SAR.
• Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU.

• Synplify Syntheses Tool From Synplicity V 5.1.4.
• Lucent Place And Route Tool Version 9.35

Company : Trenton Chip Devices
Location : Chennai, India
Designation : VLSI Design Engineer.

Project : Verification Of USB Open Host Controller
Duration : Jan' 99 - Apr'99

Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device.

• Developed the PCI Test Bench for OHCI.
• Created testcases for the functional verification of OHCI.
• Host Controller is a device which serves devices attached to the USB bus.
• It is interfaced to the PCI bus for accessing the system memory.
• Designed this core using both VHDL and VERILOG.
• This design has different types of modules.
  1. PCI Master and Target block
  2. Open Host Controller block
  3. Interface between USB and PCI side
  4. Host SIE
  5. Root Hub

Project : Design of PCI master/target.
Duration : July' 98 - Dec' 98

Designed OHCI compliant PCI master/target function.
Done testing on this module.
Carried out synthesis of all these modules using EXEMPLAR LEONARDO.
Done Place and Route using ALTERA MAX+plusII.

• PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory.
• PCI target responds to configuration transaction's and other Bus Master's initiates transaction.

• Implemented the logic for PCI Target and PCI Master.
• Tested the whole project using ModelTech simulator.
• Synthesized the logic using Exemplar's Leonardo tool.
• Max+plus II tool is used for Place and Route.
• Mapped the PCI core into the Altera Flex10k30 device.
• Mapped the USB side core into the Altera Flex10k100A device.
• Mapping the whole design into ASIC Library and testing is in progress.
• Total gate count for OHCI project is 33,000 gates.

Project : Design and verification of Hearsee-USB Logic
Duration : Jan'98 Jun'98

Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface.

• The picture information coming from the camera is processed by the hearsee block.
• This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block.
• This compressed form of data is sent through the USB cable.

• Designed the data flow for the still video capture mode of Hearse
• Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes
• Performed simulation in modeltech VHDL simulator

Project : Verification of USB Device Core
Duration : Nov' 97 - Dec' 97

Involved in the verification of a USB Device Core.

Project : Design of FIFO
Duration : Oct' 97

Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device.

Project : Design of a bit stuffer
Duration : Sep'97

Designed the bit stuffer in logic works, using VHDL and Verilog.

Project : Design of a Traffic Light Controller and Stepper Motor.
Duration : Aug' 97

Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design.

Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA.

REFERENCE : Available Upon Request.