Resume 14

Valid H1-B till 2004.

• Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols.
• Applications: Digital Design Methodology & Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities
• Languages: PERL and Shell Script, C, HTML
• CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools.
• OS: UNIX, SUN-OS, and WINDOWS

Verification Of a Re-configurable Network Processor (09/01 - present)
Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency.

Code Coverage Analysis (07/01 - 08/01)
Client: Vertex Networks, Santa Clara, CA.
My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01)
Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for better fault grading.

Design Of a CAN protocol implementation (11/00 - 01/01)
The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time.

Design Of a microcontroller (10/99 - 10/00)
The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and P&R the Timer block. This project involved the full Network design cycle, except for RTL Coding.

Design Of a 16 Bit RISC Processor (08/99 - 09/99)
It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block.

Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99)
ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation. Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project.

Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99)
SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go.

Developed a software utility, indigenously, using Perl & Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company.

American Express Milleniax Conversion (10/97 - 03/98)
The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader.

Training in Software Development Process (07/97 - 09/97)
It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database.

Advanced Chip Synthesis Workshop (2000)
The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods.

1997 B.Tech. in Electronics & Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA

Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97)
The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.