Resume 15

Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position.

• MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada.
• Ph.D. Candidate in Computer-Aided Design Center, China.
• MSCE in Computer Engineering, WU, China.
• BSEE in Electrical Engineering, WU, China.

• Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis.
• Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx.
• Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic.
• Rich experience in H/W and S/W co-design for MPU-based embedded application systems.
• In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development.
• Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS.
• Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
• Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit.

I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988.

These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies.

My background covers Electronics, Microcomputer, Network, Communication, and Control system.

Following are my some ASIC/FPGA hardware and system design experience in real world in order:

Development of a System-on-Chip ASIC for a new high-performance switching Router.

SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols.

Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design.

10GE Egress Traffic Management ASIC Design.

Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.

Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic.

• Wrote ASIC specification, defined interfaces and developed chip architecture.
• Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure.
• Partitioned core-based design and Coded in Verilog at RTL.
• Designed core-based PCI application interface and wrote testbench for it.
• Wrote simulation models and performed min. function verification for each block.
• Wrote simulation models and performed min. function verification for top level with cores.
• Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Gate level.
• Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated.
• Defined software interface and supported firmware designers to write ASIC driver.

OC3 ATM core project: ATM Traffic Executive ASIC Design.
DS3 ATM core project: ATM Traffic Executive FPGA Design.

Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope.

Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required.

• Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version.
• Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing.
• Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers.
• Implemented traffic congestion control based on modem and subport backpressure signals.
• Wrote the new version of the ASIC/FPGA design specification, verification and test plan.
• Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions.
• Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level.
• Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files.
• Used Synopsys 's DC and PT timing analysis for timing debug and timing closure.
• Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by Adtech, Smartbit.

Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000.

ATM Simulator FPGA Design Utilizing PCI Bus

VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope.

Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in real world in cooperation of EE and CS departments.

• Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09.
• Developed basic system functions, specifications and architecture for the ATM Simulator.
• Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation.
• Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL.
• Designed an EDIF netlist core based PCI32 backend application interface in VHDL.
• Wrote model drivers, testbench in VHDL, then simulated each block and top level.
• Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime.
• Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board.

Some Course Projects in VLSI and Real-time OS.

Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx.

• CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench.
• CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools.
• Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA.
• VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL.
• Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA.
• Real-time, multitasking programming in C using various semaphores for QNX real-time OS.

Development of MCU-based Controller for a graphic scanner.

Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in C.

Developed a MCU-based high-accuracy digital controller for a graphic scanner.

• Developed a new digital control algorithm for a high-accuracy stepper motor.
• Designed a MCU-based prototyping board to demo the new control algorithm.
• FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD.
• PC DOS programming and MCU 8051 firmware programming in C.

Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement.

Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware.

Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors.

• Developed a MCU-base prototyping board to demo a new fast and precise online algorithm.

Computer-based Data Acquisition Network System Development.

PC-based Application System design, Digital and Analog Board design, MCU Firmware in C.

Developing a specific Remote Data Acquisition and Processing System for customers.

• Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room.
• Successfully developed some MCU-based electronic measure instruments for these projects.
• Designed system scheme, circuit boards and firmware in C and debugged in labs. Supports.

An electronic teaching laboratory Development.

Schematic and PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C.

Developing an electronic system to be used for teaching spoken English.

• Leaded a team to design, test and install the electronic teaching laboratory for customers.
• Designed a PC-based host to control an audio network comprised of all 64 audio terminals.
• Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.

Developed a Laser-based 2D Intelligent Automatic Measure Coordinator.

HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W.

Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements.

• Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.
• Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C.

1. Advanced DC Synthesis Workshop.
2. Synopsys's VERA HVL Workshop
3. High-level Chip Design in Verilog.
4. Verification Strategies in Verilog
5. High-Speed Circuit Design.
6. Primetime Training Workshop
7. PowerPC 8260 Workshop.
8. Tornado Training Workshop

• EE6123 Semiconductor Devices ( CMOS Modeling )
• EE4173 Devices and circuits for VLSI ( CMOS IC processing )
• EE6133 VLSI Circuits Design ( analog VLSI circuits )
• EE6213 ASIC Design ( digital ASIC design )
• CS6812 Computer Aided Logic Design ( logic methodology )
• CS6845 Computer Networks and Open Systems ( IP Networks )
• EE4243 Data Communications ( Modem, Ethernet )
• EE4273 Real Time Operation of Microcomputers (RT Programming )
• EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design )
• CS4815 Advanced Computer Architecture CS5865 Data Networks II