Resume 2

Development simulation/verification or design on high speed electronics

VHDL, C, MTI simulator, ModelSim, RiscWatch debugger

• Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications.
• Designed VHDL logic code that enhanced the 603 cpu model by generating an internal address bus busy signal when an address-only phase is initiated by the ASIC.
• Developed 200+ C testcases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers.
• Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents.
• Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic.
• Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency & voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers.

• Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of data.
• Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools.
• Translated gray-code state machine and counter state graph designs into RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools.
• Developed a C code program that calculates a least-sum path of distances squared for a trade study that will implement ATM networking hardware on a RF communications data link.
• Researched and wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR & AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over a RF communications data link.

• Configured and validated the compatibility of various PCI and EISA LANs and SCSI controllers and devices on quad Pentium-Pro Servers

• Fiber Channel, ATM
• VHDL course designing a 16-bit alu w/pipelined registers
• Analog & RF/microwave theory, device physics theory, and CMOS VLSI design coursework
• COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools

ME Electrical Engineering, University of Utah, Salt Lake City, UT
BS Electrical Engineering, University of Utah, Salt Lake City, UT