Resume 4

Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. Headed the design team in the implementation of the chip. VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC.

Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. In charge of engineering development of board level designs for both product and OEM reference.

• Wrote specifications for both chip and board level products.
• Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.
• Incorporated manufacturability into designs including ATE.
• Developed and maintained project schedules.
• Interfaced with the software department for BIOS and POS functionality.

Manager of the hardware engineering team. Involved in product planning for a new family of OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions.

Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the system architecture for a second ASIC that became the system intelligence. This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners.

Managed the Raid Division engineering team. Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market.

Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering.

Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates. Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and FLASH EEPROM.

Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL.

Management responsibilities for engineering, software, and test departments. Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary "Error Detection and Correction" ASIC to be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems.

Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system. During the design phase of the CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol.

Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode.

Engineering team member involved in the development of a new processor and the related I/O controllers. Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas.

Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator.

Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s.

BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems.

Will be furnished on request.