Resume 6

Assume a role in ASIC Verification/Applications/Design Engineering

4+ years experience in the EDA Verification Industry

Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an emulation system.

• Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training & implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.
• Implemented Verification Flow. Identified & introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup.

Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution.

• Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches.

Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.

• Worked closely with Quickturn R&D and a third party R&D (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s R&D to integrate all of these products.
• Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks.

Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator.

• Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim.
• Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design.
• Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions.
• Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools.
• Presented demos and presentations at DAC 98 and DAC 00

Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including:

• Supporting Customers & Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions.
• Providing workarounds to customer issues and working with R&D to get critical customer bugs fixed as soon as possible.
• Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim.

• Modeled a MC68HC11E9 Microcontoller Unit in VHDL. The unit included microprocessor and memory components. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace.

M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96
B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94

Expertise in Cadence Simulation, Acceleration and Synthesis Tools
Experienced with ViewLogic Schematic, Design and Waveform Viewer tools

• Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE
• Emulation/Simulation Acceleration Cobalt, Radium, Palladium
• DAI: SignalScan, CompareScan
• Novas: Debussy
• Mentor Graphics: MTI
• View Logic: ViewDraw, ViewSim and ViewTrace

Strong Verilog skills, VHDL, C, Unix, Perl