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Resume 7
ABU SHALIBDAN
ASIC PHYSICAL DESIGN ENGINEER
Objective :
To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design.
Area of specialisation :
ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan,
Place & Route, Timing Verification, CTS
Summary in short :
- Have got more than 20 months of experience in the field of VLSI.
- Worked in logical design for 8 months & rest in physical design.
- Moreover i have done my academic project in VLSI field.
Professional Experience :
Arsanti! Software & Development Center(I) Pvt Ltd
Aug-2000 till date
Design Service Engineer(Physical design)
Responsiblities :
- Creating various test cases & Benchmarks for customers.
- Used to create testcases for QA of Avanti tools.
- Creating testcases to check various releases of Avanti tools.
- Clearing Customers doubts & queries regarding design & tools.
Vdesign Training & development Centre Pvt lt
Apr-2000 to Aug-2000
Trainee Design Engineer
Responsiblities :
- Logical design
- Digital design.
- Writing Verilog codes for various small Designs.
- Writing Test benches for designs.
- Writing Scripts to check the designs.
Professional Training :
- Undergone training on FPGA/ASIC design flow(logical design)
and methodology,HDL coding for circuit implementation and test
bench,simulation, timing Verification,Floorplanning,Place & Rout
-
(Vdesign Training & Development Centre, PondyCherry).
- Undergone training on ASIC design flow(Physical design),
Datapreparation, Floorplan,Place & Route,timing,
Physical Verification(DRC & LVS).
(Time To Market Ltd, Secunderabad).
Projects carried out: (Physical Design)
Java Processor :
Design Specification: Hierarchical design with 5 softmacros.
Technology : 0.24micron.
Goal Achived:
- Hierarchial Floorplanning of Top Cell with core utilization
of 75%, alongwith floorplanning of each soft macros with
utilization of 80%.
(Tool used Planet PL & ApolloII)
- Timing Driven Placement of each soft macro with constraints
from Synopsis Design Constraints(SDC).
(Tool used ApolloII & Saturn)
- Clock Tree Synthesis (CTS) of eachsoft macro with a target of
skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out
for the Top Cell also.
(Tool used ApolloII).
- Routing of each macro and the Top Cell.
(Tool used ApolloII).
- Physical Verification for DRC & LVS for each macro
and the Top Cell.
(Tool used Hercules).
Company : TTM( as a part of training program in Physical Design)
Test Cases :
- Designing of Standard Cells of 0.24 technology along
with DRC & LVS check.
(Tool used Enterprise & Hercules)
- Die Reduction & Power Analysis : With a core utilization
of 98.5%. Contains 19 hard macros, and 28k standard cells.
(Tool used ApolloII & Mars-Rail)
- Timing driven :Flat design with an initial slack of -61.3,
and congestion overflow of 4.03%.
(Tool used ApolloII & Saturn)
Bench Marks :
- BenchMark For LSI logic involving diesize with
30k std cells with core utilization of 96%.
- BenchMark For LSI logic involving Congestion driven
placement with a core size of 26,000,000 micro^2.
- Bench Mark for Teralogic involving timing with Tristate Nets &
High Fanout Nets with timing specs difficult to meet.
- Bench Mark for Teralogic involving Design Planning starting
from synthesis to Global rout
- Its mearly an analysis.
(Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)
Project(Logical design) :
EIGHT-BIT MICRO CONTROLLER
DESCRIPTION:
The microcontroller which is the true computer on chip.The
design incorporates all of the features found in a microprocessor
ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose
registers.It also has added the other features needed to make a
complete computer ie.ROM, RAM, parallel port, serial port, counter and
clk circuits Like microprocessor , microcontroller is a general
purpose device but one that is meant to read data, perform
limited calculation on that data and controls its environment
based on these calculation.
TEAM SIZE : 7 members.
DURATION : 3 months.
MY PARTS : CPU, counter & timers, Interrupts, ROM and RAM.
TOOLS USED :
- POLARIS for simulation.
- EXPLORERTL for RTL analysis.
Curriculam Project :
RTL MODEL OF FOUR BIT MICROPROCESSOR :
DESCRIPTION:
This four bit processor consists of the following components
such as multiplexer, program counter,register,instruction
decoder,ALU and timimg control,RAM and ROM .RTL code and
testbench had been written for all the above units.Various
stimuli had been given and the logic had been validated
TOOLS USED : simulator : MODEL SIM PE 5.3b
DURATION : JAN-2000 to APR-2000.
COMPANY : Vdesign, Pondycherry.
Exposure & Expertise:
| Avant! tools |
What for |
| MilkyWay |
DataPreparation. |
| ApolloII |
Place & Route. |
| Astro |
Complete Design Closure Tool. |
| Planet-PL |
Hierarchial planning |
| JupiterP |
Synthesis & Design planning. |
| Saturn |
Timing & VDSM Optimization. |
| Mars/Astro-Rail |
Power & Rail Analysis. |
| Mars/Astro-Xtalk |
X-talk Analysis. |
Curriculum Details:
- 10th Matriculation 1993 -1994 74%
- Higher Secondary 1994 -1996 81%
- B E in Electronics and Communication 1996 -2000 70%
(Affiliated to Madurai Kamaraj University, TamilNadu).
Skills:
- Hardware languages : Verilog.
- ASIC Methodologies : RTL and Behavioural.
- Assembly languages : Microcontroller.
- Software languages : C.
- Operating Systems : Unix,Windows.
- Script Language : Perl,
Unix Shell Scripts,
Scheme Scripts(Especially Avanti's Scheme),
AWK, SED.
Knowledge Base:
- Logical Design.
- Micro controller.
- Microprocessor.
Key Strengths:
- Time Conscious.
- A go-getter.
- Quest for perfection in all assignments.
Personal Details:
- Date of Birth : 02-08-1977.
- Language Known : Tamil, English.
- Nationality : Indian.
- Marital Status : Single
References :
will be provided on request.
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