Resume 8

Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment.

• Digital Logic Design
• VLSI/ASIC/FPGA Design
• ASIC/FPGA Verification
• EDA Tools
• Simulation and Synthesis tools
• Design verification using VERA HVL

• Hardware Description Language: VHDL, Verilog
• Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit
• Verification Tools: VERA Hardware Verification Language (HVL)
• EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist
• Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors
• Languages: C, C++, PERL
• Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS
• Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260

Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA.

Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim).

Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool.

Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT

Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.

There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of this design.

Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT

Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value.

Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT

Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis.

Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor.

Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1

Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required.

Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz).

Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1

Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is 1.6Gbps.

It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and Spice for analog design.

Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL.

Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1

Involved in the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of this module.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1

Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design.

Successfully tested design on power lines.

Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95

M. S. in Microelectronics and VLSI Design.