Resume 9

ASIC/FPGA Design & Verification Engineer

2.6 years of experience in FPGA Design & ASIC Verification.

• Proficient with coding RTL & Behavioral using Verilog and VHDL.
• Proficient with developing test environment for functional verification.
• Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.
• Proficient in writing fully automated test benches.
• Experience with synthesis and optimization of Verilog/VHDL code
• Experience with FPGA implementation with Xilinx.
• Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify
• Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).
• Worked on Mentor Graphics Schematic Entry Tool – Design Architect.
• Worked on PCI 32 bit @33Mhz
• Worked with Specman, an ASIC Verification tool from Verisity
• Familiar with Vera, an ASIC Verification tool from Synopsys
• Familiar with DSL Protocol.
• Familiar with ATM Protocol.
• Familiar with AMBA Bus Architecture.
• Familiar with 8085 and 8086 Architecture.
• Familiar with 8085 Assembly Language.
• Familiar with software languages C and Fortran.
• Good communication skills

Name of Project: Network Processor Verification

• Wrote test plan for one of the modules in the chip.
• Developed the test bench for the module.
• Wrote test cases in Verilog.
• Developed the different interfaces around the module.

This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric.

Tools Used : VCS & Modelsim
Language Used : Verilog

Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA

• Designed and Synthesized SWATH cycle Controller module.
• RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify
• Developed the different interfaces around the Link 2 FPGA.
• Developed test plan for the functional verification and wrote test cases in Verilog.
• Done the module level verifications and top-level verification.
• Reported bugs and worked with the design team in fixing the bugs.

This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA.

Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool).
Language Used : Verilog

Name of Project: Rrishti-1-Trace Receiver ASIC Verification

• Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level.
• Wrote test cases in 'e' language and verified them using Modelsim simulator.
• Reported several bugs in the design and worked with the designers to fix those bugs.

The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller.

The key features of the trace system ASIC are:

• Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme.
• An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.
• On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data.
• trace packet width from 1 to 20 bits
• 167 MHz processing rate

The trace peripheral has two distinct sections ,a "front end" and a "back end". The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers.

Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool).
Language used : VHDL (RTL), e language for test cases.

Name of Project : PCI based high speed data acquisition card for signal Processing

• Designed the Hardware .
• Designed the FPGA& CPLD .
• Done the functional simulation & synthesis.
• Done extensive timing simulation with back annotating the sdf.
• Done schematic Entry using Mentor Graphics Tool.

PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time.

The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory.

FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the back end. Here we place and route the design and generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and the sdf file and simulate.

Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA.

Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place & Route).
Language : VHDL

Project Title: VHDL Model of UART

• Developed the architecture
• Designed and done RTL coding in VHDL.
• Done the functional simulation, synthesis and mapped to the target PLD

Tool Used : WARP 4.1
Simulator used : NOVA
Host Platform : PC under Win95
Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)

• Study in detail one Standard HDL
• Study in detail about the PLDs
• Write own HDL code to build a model of one Standard UART chip with defined requirements
• Simulate the code for functional verification
• Synthesize and map the design to a suitable PLD.

• 10.1995 - 05.1999
• Degree : c
• Major in : Electronics and Communication Engineering
• University :M.G University Kerala, INDIA .

• Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project.
• Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance & valuable contribution to the verification of Rrishti-1.

Doing part-time courses in San Jose University for
Course 1- Advanced Logic Design (Winter 2001)
Course2-VLSI Design I (Winter 2001).
Course3-Logic Design using HDL- Project- Bluetooth Transmitter
Course4-Logic Synthesis- Done using Synopsys DC