• Logical design
• Digital design.
• Writing Verilog codes for various small Designs.
• Writing Test benches for designs.
• Writing Scripts to check the designs.

• Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place & Rout
• (Vdesign Training & Development Centre, PondyCherry).
• Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place & Route,timing, Physical Verification(DRC & LVS). (Time To Market Ltd, Secunderabad).

Design Specification: Hierarchical design with 5 softmacros.
Technology : 0.24micron.
Goal Achived:

• Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL & ApolloII)
• Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII & Saturn)
• Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. (Tool used ApolloII).
• Routing of each macro and the Top Cell. (Tool used ApolloII).
• Physical Verification for DRC & LVS for each macro and the Top Cell. (Tool used Hercules).

• Designing of Standard Cells of 0.24 technology along with DRC & LVS check. (Tool used Enterprise & Hercules)
• Die Reduction & Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII & Mars-Rail)
• Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII & Saturn)

• BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%.
• BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2.
• Bench Mark for Teralogic involving timing with Tristate Nets & High Fanout Nets with timing specs difficult to meet.
• Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout
• Its mearly an analysis.

(Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)

DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on that data and controls its environment based on these calculation.

TEAM SIZE : 7 members.
DURATION : 3 months.
MY PARTS : CPU, counter & timers, Interrupts, ROM and RAM.
TOOLS USED :

• POLARIS for simulation.
• EXPLORERTL for RTL analysis.

DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated

TOOLS USED : simulator : MODEL SIM PE 5.3b
DURATION : JAN-2000 to APR-2000.
COMPANY : Vdesign, Pondycherry.

• 10th Matriculation 1993 -1994 74%
• Higher Secondary 1994 -1996 81%
• B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu).

• Hardware languages : Verilog.
• ASIC Methodologies : RTL and Behavioural.
• Assembly languages : Microcontroller.
• Software languages : C.
• Operating Systems : Unix,Windows.
• Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED.

• Logical Design.
• Micro controller.
• Microprocessor.

• Time Conscious.
• A go-getter.
• Quest for perfection in all assignments.

• Date of Birth : 02-08-1977.
• Language Known : Tamil, English.
• Nationality : Indian.
• Marital Status : Single

Up

Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment.

• Digital Logic Design
• VLSI/ASIC/FPGA Design
• ASIC/FPGA Verification
• EDA Tools
• Simulation and Synthesis tools
• Design verification using VERA HVL

• Hardware Description Language: VHDL, Verilog
• Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit
• Verification Tools: VERA Hardware Verification Language (HVL)
• EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist
• Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors
• Languages: C, C++, PERL
• Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS
• Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260

Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA.

Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim).

Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool.

Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT

Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.

There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of this design.

Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT

Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value.

Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT

Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis.

Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor.

Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1

Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required.

Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz).

Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1

Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is 1.6Gbps.

It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and Spice for analog design.

Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL.

Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1

Involved in the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of this module.

Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1

Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design.

Successfully tested design on power lines.

Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95

M. S. in Microelectronics and VLSI Design.

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ASIC/FPGA Design & Verification Engineer

2.6 years of experience in FPGA Design & ASIC Verification.

• Proficient with coding RTL & Behavioral using Verilog and VHDL.
• Proficient with developing test environment for functional verification.
• Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.
• Proficient in writing fully automated test benches.
• Experience with synthesis and optimization of Verilog/VHDL code
• Experience with FPGA implementation with Xilinx.
• Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify
• Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).
• Worked on Mentor Graphics Schematic Entry Tool – Design Architect.
• Worked on PCI 32 bit @33Mhz
• Worked with Specman, an ASIC Verification tool from Verisity
• Familiar with Vera, an ASIC Verification tool from Synopsys
• Familiar with DSL Protocol.
• Familiar with ATM Protocol.
• Familiar with AMBA Bus Architecture.
• Familiar with 8085 and 8086 Architecture.
• Familiar with 8085 Assembly Language.
• Familiar with software languages C and Fortran.
• Good communication skills

Name of Project: Network Processor Verification

• Wrote test plan for one of the modules in the chip.
• Developed the test bench for the module.
• Wrote test cases in Verilog.
• Developed the different interfaces around the module.

This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric.

Tools Used : VCS & Modelsim
Language Used : Verilog

Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA

• Designed and Synthesized SWATH cycle Controller module.
• RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify
• Developed the different interfaces around the Link 2 FPGA.
• Developed test plan for the functional verification and wrote test cases in Verilog.
• Done the module level verifications and top-level verification.
• Reported bugs and worked with the design team in fixing the bugs.

This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA.

Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool).
Language Used : Verilog

Name of Project: Rrishti-1-Trace Receiver ASIC Verification

• Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level.
• Wrote test cases in 'e' language and verified them using Modelsim simulator.
• Reported several bugs in the design and worked with the designers to fix those bugs.

The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller.

The key features of the trace system ASIC are:

• Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme.
• An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.
• On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data.
• trace packet width from 1 to 20 bits
• 167 MHz processing rate

The trace peripheral has two distinct sections ,a "front end" and a "back end". The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers.

Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool).
Language used : VHDL (RTL), e language for test cases.

Name of Project : PCI based high speed data acquisition card for signal Processing

• Designed the Hardware .
• Designed the FPGA& CPLD .
• Done the functional simulation & synthesis.
• Done extensive timing simulation with back annotating the sdf.
• Done schematic Entry using Mentor Graphics Tool.

PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time.

The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory.

FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. We are using Xilinx tool as the back end. Here we place and route the design and generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and the sdf file and simulate.

Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA.

Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place & Route).
Language : VHDL

Project Title: VHDL Model of UART

• Developed the architecture
• Designed and done RTL coding in VHDL.
• Done the functional simulation, synthesis and mapped to the target PLD

Tool Used : WARP 4.1
Simulator used : NOVA
Host Platform : PC under Win95
Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)

• Study in detail one Standard HDL
• Study in detail about the PLDs
• Write own HDL code to build a model of one Standard UART chip with defined requirements
• Simulate the code for functional verification
• Synthesize and map the design to a suitable PLD.

• 10.1995 - 05.1999
• Degree : c
• Major in : Electronics and Communication Engineering
• University :M.G University Kerala, INDIA .

• Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project.
• Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance & valuable contribution to the verification of Rrishti-1.

Doing part-time courses in San Jose University for
Course 1- Advanced Logic Design (Winter 2001)
Course2-VLSI Design I (Winter 2001).
Course3-Logic Design using HDL- Project- Bluetooth Transmitter
Course4-Logic Synthesis- Done using Synopsys DC

Up

Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth.

• H/W Description Languages: VHDL, Verilog.
• Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance.
• Synthesis: Exemplar logic (Leonardo Spectrum).
• Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms).
• Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.
• Languages: C, C++, perl, Unix Internals like Shell and Awk.
• Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98.
• Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF
• Others: PCI.
• Revision Control: CVS.

As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.

Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage.

• Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy.
• Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments.
• Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality.
• Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c .
• Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment.
• Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block.
• Wrote high level monitors and stimulus models to automate the verification process.
• Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform.
• Wrote Scripts for HEP (Hardware Emulation Platform) regression suites.
• Participated in estimating verification development schedules and ensured on time delivery.

As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the digital portion of the chip for television.

• Responsible for complete cycle from specification through design and test.
• Designed the digital circuit using VHDL.
• Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.
• Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA.
• Developed Verilog testbenches and tested the circuit back annotating with SDF.
• Checked the timing of the design generating test vectors for testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL.
• I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface.
• Designed a I2C bus slave interface controller using Visual HDL.
• Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.
• Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and tested the read channel chip.
• Worked on three different versions of the read channel.
• Designed the FPGA using Visual HDL generating the RTL for the design.
• Tested the design writing VHDL test benches for the proper operation
• Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.
• Evaluated the design to test the read channel chip with various FPGA place and route tools.
• Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.
• Designed an IEEE standard TAP controller.
• Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL.
• Simulated it using Modelsim. Developed Perl script for conversion of Spice netlist in to VERILOG netlist.
• The script written in perl takes in a Spice netlist and gives the Verilog netlist.
• Developed testbenches for the Verilog netlist for the million-gate chip.
• Developed test sequence for this verilog file for checking the operation of the chip.

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000.
GPA: 3.727/4.0.

Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming.

• Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects
• Design of a Linear Interpolation Filter using Verilog and full custom IC layout.
• Design of a Simple Educational Processor using VHDL.
• Designed and simulated a sigmadelta modulator for an EEG IC.

Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998.
GPA: 80.5%

Up

ASIC-FPGA Design & Verification Engineer

To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole.

Over 7+ years of experience 5+ years of experience in Hardware Design, Development & Verification using ASIC, PLD, CPLD & FPGA Designing & Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator & Programming of RAM(SRAM & DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and able to work in a team.

Bachelor of Electrical Engineering from Bangalore University.

Jan 2000 - Present DSSABC Software, Inc., CA, USA
Feb 1998 - Nov 1999 FDD Containers Limited, London, UK
Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya
Jul 1994 - Sep 1996 Advanced Systems & Solutions, Delhi, India

Scope of the project was to design & develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally & Supports Gigabit Ethernet on Fiber Optics.

• FPGA & ASIC design
• Wrote verilog HDL code for design.
• Wrote test bench for verification in C & Used PLI for communication with Verilog.
• Integration testing & verification.
• Functional testing & verification.

Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys

The objective of this project was to design, developed the data networking boards and test benches for verification purpose of pre written functions in verilog .

• Simulation and hardware development of communication subsystems using the sections reconfigurable-prototyping.
• Design, simulate, and test digital hardware.
• Developed data networking boards, and backplanes.
• Performed the design, capture the schematics and oversee the board layout.
• Performed board simulation and signal integrity

Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks

FDD Containers Limited, London, UK [Feb 1998 - Nov 1999]

The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed & implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. The code was written in c & inline Assembly on Host Computer.

• Design, simulate, and test.
• Programming of SRAM & DRAM.
• Writing Test Benches for Verification in verilog & C.
• Performed board simulation

Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.

The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c & inline assembly. Device programmer was used to copy the image files on the chip.

• Design, simulate, and test micro controller chip.
• Programmed SRAM & DRAM.
• Wrote verification code in verilog & C
• Performed the design, capture the schematics and oversee the board layout.
• Performed board simulation

Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.

RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97]

DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions & related data Information that is also capable of modifying as per the user specifications and standards. It takes the Complete Details of a building (to be constructed) by providing an Interface and Calculates the quantity of material required with its estimated cost, as per the standards specified. It provides an easy access for modifications.

Environment: C, UNIX and MS DOS.

Smart Systems & Solutions, Delhi, India [Jul 1994 - Sep 1996]

A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired.

Environment: Visual C++, MS Windows 95.

An Application Program of which the Core Part is handled using C++, and the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT. Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility.

• It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time.
• Provides an Easy and Quick File Search.
• Provides Quick Access to file Opening and Executing.
• Provides File Viewing facility before editing the files, giving an Easy access to Editing.

Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95.

"Impress" is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section & Camera Section). Was a member of the team, which designed the system? Other responsibilities included coding and testing. Developed 12 forms and various other Reports.

Environment: Visual C++, Visual Basic, MS Windows 3.1

Visa Status : H1B

Up

Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol.

• Hardware Description Languages: Verilog, VHDL
• High Level Verification Language: Synopsis VERA
• CVE: Mentor Graphics Co-Verification Environment
• Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell
• Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C
• OS: Sun Solaris, Unix, Windows 95/NT

Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . These modes are the local bus types. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed.

Environment: Verilog, Sun Solaris

Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors.

Environment: Verilog, CVE, Assembly, Sun Solaris 2.x

The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules.

The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs.

Environment: Verilog, VERA, VCS, Sun Solaris 2.x

Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC. Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes.

Environment: Verilog, Assembly, VCS, Unix

Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs.

Environment: Verilog, Verilog -XL, Sun Solaris 2.x

Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC. Synthesized the HDLC.

Environment: Verilog, Verilog-XL, Sun Solaris 2.x

Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation.

Environment: VHDL, Quick HDL, Unix

This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made.

Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix

Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard.

Environment: Assembly, Unix

Up

To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place & route, FPGA and CHIP layout.

• VLSI Logic design - Complete design flow from RTL to layout.
• Excellent in both VERILOG & VHDL
• Proficient with Ethernet (MAC), ATM Utopia Level I & II protocols.
• Complete understanding in architectures of PCI & OHCI.
• Proficient with USB.
• Knowledge in Unix, Perl and 'C'.
• Knowledge in VERILOG PLI CONCEPTS.
• Good experience in Digital synthesis and Place & Route.
• Configuring CPLD with bit blaster using MAX+plus II.
• Expertise in Altera /APEX FPGA.
• Experience in Assembly Language.
• Analyzed circuits using SPICE.

• Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL & Verilog), Leapfrog Simulation for VHDL & Accolade Peak VHDL tools.
• Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity.
• P & R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics.
• Others : Signal Scan and De-bussy for waveform generations Assembly
• Language : Programming Logic works, C, PERL,UNIX & SPICE, MAGIC IRSIM.
• 'C' Compiler : Green Hills Software

Company I : Analog Systems, CA.
Duration : Jan '00 - Till Date
Designation : Member Of Technical Staff

Company II : Trenton Chip Devices, Inc., CA
Duration : May '99 - Dec '99
Designation : VLSI Design Engineer

Company III : Trenton Chip Devices, India
Duration : May '97 - Apr '99
Designation : VLSI Design Engineer

Profile I :

Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution
Duration : August 2000 - Till Date.

The Si was taped out on Oct '2001. The Total No. of gates is 1.2 Millions. It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small & Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP & VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system.

It is having 3 processors namely Control Processor Engine, Wan Processor Engine & Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, & SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI & USB. It has on chip SDRAM controller & flash controller 200KB of on-chip memory for voice and data processing.

• Developed & Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams.
• Created Testbenchs for the blocks like UART, SPI & DMA.
• Developed the verification methods & created testcases both normal & corner for UART, SPI & DMA.
• Did the RTL & netlist simulation for UART, SPI, DMA.
• Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL & netlist level simulations.
• Did the random testing for the above blocks at the system levels and also for the other blocks.

Tools Used :

Project : UMAC Design
Duration : Feb' 00 - July '00.

Designed, developed & verified the UMAC in VERILOG. This s going to be used and cable modem chip. The design was target for APEX FPGA from altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.

The PHY interface can get the data from simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from memory and gives to the microprocessor module.

The design operates in 3 different frequencies. The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz.

Verilog XL from Cadence 2.37 & Signal Scan/De-bussy for waveforms. Max-Plus II for P & R. Synthesis by Syniplify from synplicity.

Project : SPI Design
Duration : Jan '00.

Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA.

Tools Used :

Profile II :

Project : Transceiver Subsystem
Duration : Nov'99 - Dec '99

Designed & Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the code in Verilog.

Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics

Project : Internet Data Storage
Duration : Aug'99 - Oct'99

To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated.

The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Developed & Designed the logic in verilog which is specific to Disk Module and it provides the following functions:

• Raid Parity generation
• Raid Parity verification
• Raid Parity reconstruction
• Interface to the Main Memory DMA

Compiled and simulated in MTI Verilog simulator (Model Tech).

Project : OC3_FPGA
Duration : May'99 - July'99

The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported.

• Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target.
• Module ware Utopia Master and Slave.
• Interface Data Path Between Tetra and SAR.
• Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU.

• Synplify Syntheses Tool From Synplicity V 5.1.4.
• Lucent Place And Route Tool Version 9.35

Company : Trenton Chip Devices
Location : Chennai, India
Designation : VLSI Design Engineer.

Project : Verification Of USB Open Host Controller
Duration : Jan' 99 - Apr'99

Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device.

• Developed the PCI Test Bench for OHCI.
• Created testcases for the functional verification of OHCI.
• Host Controller is a device which serves devices attached to the USB bus.
• It is interfaced to the PCI bus for accessing the system memory.
• Designed this core using both VHDL and VERILOG.
• This design has different types of modules.
  1. PCI Master and Target block
  2. Open Host Controller block
  3. Interface between USB and PCI side
  4. Host SIE
  5. Root Hub

Project : Design of PCI master/target.
Duration : July' 98 - Dec' 98

Designed OHCI compliant PCI master/target function.
Done testing on this module.
Carried out synthesis of all these modules using EXEMPLAR LEONARDO.
Done Place and Route using ALTERA MAX+plusII.

• PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory.
• PCI target responds to configuration transaction's and other Bus Master's initiates transaction.

• Implemented the logic for PCI Target and PCI Master.
• Tested the whole project using ModelTech simulator.
• Synthesized the logic using Exemplar's Leonardo tool.
• Max+plus II tool is used for Place and Route.
• Mapped the PCI core into the Altera Flex10k30 device.
• Mapped the USB side core into the Altera Flex10k100A device.
• Mapping the whole design into ASIC Library and testing is in progress.
• Total gate count for OHCI project is 33,000 gates.

Project : Design and verification of Hearsee-USB Logic
Duration : Jan'98 Jun'98

Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface.

• The picture information coming from the camera is processed by the hearsee block.
• This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block.
• This compressed form of data is sent through the USB cable.

• Designed the data flow for the still video capture mode of Hearse
• Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes
• Performed simulation in modeltech VHDL simulator

Project : Verification of USB Device Core
Duration : Nov' 97 - Dec' 97

Involved in the verification of a USB Device Core.

Project : Design of FIFO
Duration : Oct' 97

Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device.

Project : Design of a bit stuffer
Duration : Sep'97

Designed the bit stuffer in logic works, using VHDL and Verilog.

Project : Design of a Traffic Light Controller and Stepper Motor.
Duration : Aug' 97

Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design.

Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA.

REFERENCE : Available Upon Request.

Up

Valid H1-B till 2004.

• Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols.
• Applications: Digital Design Methodology & Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities
• Languages: PERL and Shell Script, C, HTML
• CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools.
• OS: UNIX, SUN-OS, and WINDOWS

Verification Of a Re-configurable Network Processor (09/01 - present)
Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency.

Code Coverage Analysis (07/01 - 08/01)
Client: Vertex Networks, Santa Clara, CA.
My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01)
Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for better fault grading.

Design Of a CAN protocol implementation (11/00 - 01/01)
The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time.

Design Of a microcontroller (10/99 - 10/00)
The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and P&R the Timer block. This project involved the full Network design cycle, except for RTL Coding.

Design Of a 16 Bit RISC Processor (08/99 - 09/99)
It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block.

Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99)
ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for the full chip simulation. Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project.

Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99)
SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go.

Developed a software utility, indigenously, using Perl & Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company.

American Express Milleniax Conversion (10/97 - 03/98)
The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader.

Training in Software Development Process (07/97 - 09/97)
It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database.

Advanced Chip Synthesis Workshop (2000)
The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods.

1997 B.Tech. in Electronics & Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA

Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97)
The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Up

Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position.

• MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada.
• Ph.D. Candidate in Computer-Aided Design Center, China.
• MSCE in Computer Engineering, WU, China.
• BSEE in Electrical Engineering, WU, China.

• Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis.
• Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx.
• Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic.
• Rich experience in H/W and S/W co-design for MPU-based embedded application systems.
• In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development.
• Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS.
• Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.
• Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit.

I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988.

These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development,